Accompanied by the development of technologies and the increasing demands for data and code memory, electrically erasable programmable memory (EEPROM) is widely used due to its programmable and erasable features. As a type of flash memory, it has witnessed an increasing application in semiconductor field due to its erasing speed and high availability. Normally, a flash memory has a structure of split gate or stacked gate or the combination. Wherein, the split gate structure has more extensive application owing to such advantages as high programming efficiency and prevention of “over erasing”. Self-aligned split gate flash memory is a type of split gate flash memories, which can alleviate the difficulty in photolithographic alignment and improve the integration by means of self alignment. It is known as self-aligned split gate flash memory, the structure of which is shown in FIG. 1: it has a control gate 11 and a floating gate 12, a source 13 and a drain 14, a source polysilicon region 15, and an insulation region 16. In this structure, the channel below the control gate 11 and the channel below the floating gate 12 are in series connection. F-N tunneling between the floating gate 12 and the control gate 11 is used for erasing; whereas hot carrier injection at the source terminal serves as the approach for programming. During programming, a high voltage is imposed on the source 13 to produce channeling hot carriers. The overlapped part between the source diffusion region and the floating gate 12 couples a high voltage to the floating gate 12, and thereby generating an electric field from the floating gate 12 toward the channel to attract hot carriers. Therefore, the voltage on the floating gate 12 is of vital importance to the programming efficiency.
Such manufacturing method has been confronted with obvious problems with the reduction in the minimum size. In order to manufacture more flash memory units within the same area, the minimum size for photolithography and the dimension of elements shall be further reduced with development of technologies; whereas the length of the floating gate shall be shortened accordingly. Furthermore, the size of the source diffusion region shall also be reduced to prevent the channel below the floating gate from breakdown. As a result, the voltage coupled from the source terminal to the floating gate is decreased, and the programming efficiency is reduced. Moreover, accompanied by reduced size of the source polysilicon, the resistance of the source polysilicon wire is increased, and the reading current of the memory unit is reduced.
To keep the programming efficiency, one method is to add a second control gate above the floating gate. This kind of structure as shown in FIG. 2 is called a self-aligned tri-gate split gate flash memory, which comprises a first control gate 21 and a floating gate 22, a source 23 and a drain 24, a source polysilicon region 25 and an insulation region 26; furthermore, a second control gate 27 is formed above the floating gate 22. During programming, a high voltage is imposed on the second control gate 27 to increase the voltage on the floating gate 22. However, such method may result in increased complexity in circuit design and manufacturing process, as well as increased manufacturing cost.